Lecture 7 Intro to RISC-V

Assembly Language

1. Different CPU implement different sets of instructions.
2. The set of instructions a particular CPU implements is an ISA (Instructions Set Architecture).

Examples of ISAs

• ARM (cell phones)
• Intel x86 (i9, i7, i5, i3)
• IBM/Motorola PowerPC (old Macs)
• MIPS
• RISC-V

RISC philosophy

• RISC: Reduced Instruction Set Computer
• Keep the instruction set small and simple, makes it easier to build fast hardware

RISC-V

1. Assembly Operands are registers
   • Registers are limited number of special locations, built directly into the hardware
   • RISC-V: Operations can only be performed on register operands
2. In Assembly Language, there's no type for registers
   • Register contents are just bits
   • Operation determines type, i.e., how register contents are treated

Since registers are inside the processor and directly into the hardware, it's super fast.

32 Registers in RISC-V

RISC-V code must be very carefully put together to efficiently use registers

• Each RISC-V register is 32 bits wide.
  • Groups of 32 bits called a word
• Referred to by number x0 – x31
  • x0 is always 0
  • only 31 registers able to hold variable values

Syntax Presentation in RISC-V

1. Each statement is an instruction
2. Each line of assembly code contains at most 1 instruction
3. Syntax is rigid
   • 1 Operator
   • 3 Operands

format:

opname rd, rs1, rs2

// opname: operator, by name
// rd: destination register (operand getting result)
// rs1: source register 1 (1st operand)
// rs2: source register 2 (2nd operand)

In-line comments prefixed by #, no multi-line comment support:

# add x10, x1, x2 
# add x10, x10, x3 
# sub x10, x10, x4

Basic

add / sub / addi / subi(X)

(1) add:

add x1, x2, x3

(2) sub:

sub x4, x5, x6

(3) addi:

addi x3, x4, 10

# Syntax similar to add instruction. 
# But the last operand must be a number, not a register.

(4) subi(X):

There is no subi in RISC-V, but we can use (addi + negative number) to implement subi:

addi x3, x4, -10

(5) RISC-V hardwires the register x0 to value 0:

addi x3, x0, 0xff
addi x4, x0, 0x100

addi x0, x3, x4

Here we can find x0 is still 0, the last instruction will do nothing :)